1. Field of the Invention
The embodiments discussed herein relate to a semiconductor device and method of manufacturing a semiconductor device used as a switching device formed on a silicon carbide substrate.
2. Description of the Related Art
FIG. 19 is a cross-sectional view of a conventional n-channel MOSFET formed using a silicon carbide substrate. An n−-type SiC layer 2 having a low impurity concentration is formed on a front surface side of an n-type silicon carbide (SiC) substrate 1 and p-type base regions 10 are formed in a surface layer of the n−-type SiC layer 2. P-type SiC layers 11 are further formed on the surface of the p-type base regions 10. On the front surface of the n−-type SiC layer 2 where no p-type base region 10 is formed, an n-type region 12 is formed between the p-type SiC layers 11. A p+-type contact region 5 of a high impurity concentration and an n-type source region 4 are formed in the p-type SiC layers 11. A source electrode 8 is formed on a front surface of the n-type source region 4 and the p+-type contact region 5. On a surface of a portion of the p-type SiC layer 11 between the n-type region 12 and the n-type source region 4, a gate electrode 7 is formed from the p-type SiC layer 11 to the n-type region 12, via a gate insulating film 6. A drain electrode 9 is formed on a back surface side of the n-type SiC substrate 1 (for example, refer to Japanese Patent Application Laid-Open Publication No. H8-186254).
In the MOSFET of the structure depicted in FIG. 19, when a positive voltage with respect to the source electrode 8 is applied to the drain electrode 9 and a voltage lower than the gate threshold is applied to the gate electrode 7, a pn junction between the p-type base region 10 and the n−-type SiC layer 2, or between the p-type SiC layer 11 and the n-type region 12 is reverse biased and therefore, current does not flow. On the other hand, when voltage equal to or higher than the gate threshold is applied to the gate electrode 7, an inversion layer is formed at the surface of the p-type SiC layer 11 or the p-type base region 10 immediately beneath the gate electrode 7 whereby, switching operation of the MOSFET by the voltage applied to the gate electrode 7 is enabled.